1. Field of the Invention
This invention relates to the field of semiconductor testability and in particular to the insertion of latches into a semiconductor logic circuit to provide testing sites.
2. Background Art
It is well known that after digital logic circuits are manufactured, it is necessary to test the circuits for reliability. Prior to the type of testing called scan/set testing, digital logic networks were testable using only real edge pins. The real inputs were given logical values, and the logical functioning of the digital network was simulated with software to determine the proper output logic values.
During this simulation, digital logic failures were modeled to emulate the conditions of real hardware failures which may later be detected during testing of the logic networks. This was called fault simulation. Fault simulation was a complicated and time-consuming process. The ability of a software simulation to emulate a faulty network has depended upon both the overall size of the logical network being simulated and the number of buried sequential latches within the network. Buried sequential latches are latches whose inputs and outputs are not connected to any real edge pins.
In testing using fault simulation, all of the functions which the circuit was designed to perform were exercised to determine whether they operated properly. However, this method of testing may leave areas of a circuit untested and thus, not observable. The problem of lack of observability within circuits has increased with the greatly increased density of logic circuitry. As density increased, the number of internal logic elements per external pin increased, making it more difficult to properly simulate network faults.
It is known in the art to insert additional circuitry at a plurality of points within the circuit to be tested to serve as test sites within the circuit under test. These test sites may receive and store information from a single external pin. The stored information may be applied to the circuit under test. These sites may also receive information from the circuit under test and apply it to an external pin. Thus these sites may serve as "virtual pins" and improve testability over what was previously available using only real edge pins. U.S. Pat. No. 3,783,254 issued to Eichelberger and U.S. Pat. No. 4,293,919 issued to DasGupta teach the insertion of latches for testing purposes.
In these and similar systems, there was a partitioning of the logic circuits using inserted latches in which the inserted latches were coupled with preexisting latches and were positioned within the circuit under test in such a way as to divide the circuit under test and to form boundaries of partitions of the circuit under test. This had the dual effect of reducing the size of the logic network that was fault simulated and reducing the number of buried sequentials in the logic network. The size of the logic network was reduced because the inserted latches, coupled with the preexisting latches, served as scan/set latches and served as partitioning break points which divided a single large logic network into many smaller logic networks. The number of sequentials within the network was reduced because some of the buried sequential latches were converted to scan/set latches which fell between the partitions and were not fault simulated.
Shift registers were then formed by joining the inserted scan/set latches together. Scan data was shifted through the shift registers to apply test data to predetermined sites in the logic circuits under test. Additionally, data from the logic circuits could be latched into the shift registers. This data which was received from the logic circuits into the registers was shifted through the registers to a dedicated external output pin where it could be analyzed for fault diagnosis. Design for Testability of the IBM System /38 by L. A. Stolte, Proc. 20th IEEE Test Conference, October, 1979 and Designing LSI Logic for Testability by E. I. Muehldorf, Proc. 7th Semiconductor Test Conference, October, 1976 describe this type of improvement in testability.
Using these methods, many of the partitions became purely combinatorial in that they did not contain any buried sequential latches. However, not all buried sequentials were converted to scan/set latches and some of the logic partitions contained buried sequential latches.
In these prior test systems, the conventional preexisting latch was coupled to a data selector allowing the latch to accept either system data or scan/set data depending on whether the system clock or the scan/set clock was pulsed. This latch was coupled to a slave latch to create a virtual pin. These virtual pins could only be inserted at locations where the preexisting latch was present because the preexisting latch and the inserted latch operated cooperatively to form the virtual pin. Thus the number and location of virtual pins which could be inserted to test systems using this method were limited because virtual pins could be formed only where there was a preexisting latch. Consequently, the partitioning of the circuits under test was constrained because boundaries could only be formed where there were preexisting latches.
Furthermore, the operation of the virtual pin during testing of the circuit under test was partly controlled by the system clock. This resulted from the fact that one of the latches of the virtual pin, i.e. the preexisting latch, was also part of the partitioned circuit and required the system clock input for normal system functions. Thus it was not possible to use the system clock input to the existing latch completely independently.
It is therefore an object of the present invention to provide a virtual pin for testing logic circuitry which may be inserted in the quantity and at the locations required for optimum testability independently of the existing circuitry of the logic circuit to be tested.
It is a further object of the present invention to provide a virtual pin for testing logic circuitry which may be controlled during testing by signals which are independent of the system clock.